(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing surface damage after the process of Chemical Mechanical Polishing (CMP) has been completed.
(2) Description of the Prior Art
Current semiconductor technology continues to improve device performance by reducing device feature dimensions and by providing denser packaging for the devices, reducing the length of inter-device interconnects. Parasitic influences are therewith reduced as are induced ohmic losses over interconnect lines.
Semiconductor device technology has progressed from Large Scale Integration (LSI) through Very Large Scale Integration (VLSI) to the present Ultra Large Scale Integration (ULSI). This technological evolution has affected not only devices and device features but has in addition greatly affected the manner and methods that are used to interconnect semiconductor devices and to package these devices once the devices are created.
Semiconductor devices that are created using VLSI technology contain a large variety of semiconductor and electrical components such as transistors of significantly different designs, resistors, capacitors and inductors that are formed on a chip that also contains digital processing capabilities, digital devices and analog devices with hybrid devices that process both digital and analog data. All of these devices however have in common that devices and device features must be interconnected before the device can be considered a complete, functional device. Processing dimensions of patterns that are created for the purpose of creating a semiconductor device have been decreasing year by year and are approaching submicron dimensions. Key to the creation of good interconnect metal is the planarity or surface flatness of the interconnect metal. This aspect of the creation of interconnect lines takes on even more urgency in applications where multiple layers of interconnect lines and line patterns are superimposed. Lack of planarity in a lower layer is in those cases further multiplied, this to the point where higher layers of interconnect become impossible to create (due to poor depth of focus for the photolithographic process that is required for the creation of these layers). To address this problem of surface planarity, a method of planarization, that is Chemical Mechanical Polishing or CMP, has been developed. A CMP technique is one of the techniques that has been developed to meet strict requirements for surface planarity as it applies to further device miniaturization. This technique is essential in performing planarization of insulating layers that are formed between overlying layers of conducting interconnect lines, for the formation of plugs, for the formation of buried metal interconnections and for the isolation of buried elements in semiconductor devices. The process of CMP is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate.
The use of chemical mechanical polishing to planarize semiconductor substrates has not met with universal acceptance, particularly where the process is used to remove high elevation features created during the fabrication of microelectronic circuitry on the substrate. One primary problem, which has limited the used of chemical mechanical polishing in the semiconductor industry, is the limited ability to predict, much less control, the rate and uniformity at which the process will remove material from the substrate. As a result, CMP is a labor intensive process, because the thickness and uniformity of the substrate must be constantly monitored to prevent over-polishing or inconsistent polishing of the surface of a substrate.
Current polishing practice uses a slurry that is inserted between the polishing medium, such as a polishing pad and the surface that is being polished. The slurry is primarily used to enhance the rate at which selected materials are removed from the substrate surface. It is basic that the slurry must be present in equal amount and having equally abrasive polishing characteristics across the surface that is being polished. This because it is highly desirable that the polishing of a semiconductor surface proceeds in a uniform and even manner across the surface that is being polished. To add further complexity to this requirement it must be realized that the polishing medium and the surface that is being polished are typically urged towards each other in order to enhance the abrasive polishing action. This urging together of the two surfaces makes an even distribution of the slurry that must be present between these surfaces even more difficult. One factor, which contributes to the unpredictability and non-uniformity of the polishing rate of the CMP process, is the non-homogeneous replenishment and therefore the non-homogeneous polishing action of slurry at the surface of the substrate and the polishing pad. The slurry, which is in contact with the substrate, reacts with selected materials on the surface of the substrate. As a result of this reaction the slurry becomes less abrasive and the polishing enhancing characteristics of the slurry are significantly altered. One approach to overcoming this problem is to continuously provide fresh slurry onto the polishing pad. Fresh slurry must, in order to achieve uniform polishing action across a surface, be present across this surface in equal amounts on all points of the polished surface.
In a typical CMP apparatus a polishing pad is attached to a circular polishing table, which rotates at a rate in the order of 1 to 100 m RPM. A wafer carrier is used to hold a wafer face down against the polishing pad. The wafer is held in place by applying a vacuum to the backside of the wafer. The wafer carrier also rotates, usually in the same direction as the polishing table, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table, the wafer traverses a circular polishing path over the polishing pad. A force is also applied in the downward vertical direction against the wafer, which presses the wafer against the polishing pad as it is being polished. The force is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft that is attached to the back of wafer carrier. Slurry is provided to the top of the polishing pad to further enhance the polishing action of polishing pad. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
When applying the CMP process to Intra Level Dielectric (ILD) and Inter Metal Dielectric (IMD) that are used for the manufacturing of semiconductor wafers, surface imperfections (micro-scratch) typically present a problem. Imperfections caused by micro-scratches in the ILD and IMD can range from 100 to 1000 EA for 200 mm. wafers, where an imperfection typically has a depth from 500 to 900 xc3x85 and a width of from 1000 to 3000 xc3x85.
It is clear that the impact that the presence of micro-scratch has on the surface of an interconnect medium is dependent on the size of the interconnect medium. For the larger size devices within the semiconductor wafer, with dimensions of the interconnect lines of 0.35 xcexcm or larger, the impact of micro-scratch may be relatively mild. For device sizes in the semiconductor wafer of 0.25 xcexcm or less, micro-scratch may result in relative large imperfections in the surface of the wafer, large with respect to the size of the semiconductor devices. These imperfections will cause shorts between the metal lines in the devices while the imperfections also have a severe negative impact on device yield and device reliability.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines, since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. Poor copper gap fill together with subsequent problems of etching and planarization are suspected to be the root causes of these problems. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
CMP scratch, surface dishing and surface erosion are critical aspects of surface planarization for the environment where dielectrics (in which an interconnect pattern is created) having a low-k dielectric constant are used with copper as an interconnect metal. Oxide has long been used as an Intra Metal Dielectric (IMD) or Inter Level Dielectric (ILD), oxide is more resistant to the process of CMP due to its (harder) molecular structure. Dielectrics that have a low-k dielectric constant are typically softer than oxide and therefore have different polishing characteristics than oxide when subjected to the process of CMP. The invention addresses the concern of polishing copper surfaces that are created in and therefore surrounded by low-k dielectric materials.
Referring now to FIG. 1, there is shown a cross section of a semiconductor surface 10 over the surface of which a pattern of interconnect lines 12 has been created, pattern 14 has been highlighted as part of the interconnect metal that has been created on the surface of layer 10. The distinction between patterns 12 and 14 is made in order to highlight the difference in CMP characteristics that may arise due to the difference in pattern density between patterns 12 and 14. Semiconductor surface 10 is typically the surface of a silicon semiconductor substrate, interconnect pattern 12 is typically the pattern of interconnect lines while pattern 14 is typically the pattern of a contact pad. A layer 16 of dielectric has been deposited over the semiconductor surface 10, including the surface of the interconnect pattern 12 and 14. Due to the difference in pattern density between patterns 12 and 14, it is to be expected that removal or polishing of the layer 16 of dielectric proceeds differently in the surface region of layer 16 that overlays pattern 12 as opposed to the surface region that overlays pattern 14. Also, layer 16 must be deposited to a thickness that is adequate to prevent dishing of the surface of the layer 16 of dielectric in the large surface area of layer 10 that separates the pattern 12 from the pattern 14. It is from this to be expected that it is a challenge to polish the surface of layer 16 in such a manner that good planarity is achieved across the patterns 12 and 14. It is the objective that, after the polishing of the surface of layer 16 has been completed, a thin protective layer remains in place overlying both patterns 12 and 14. This layer forms the protection of the surface of patterns 12 and 14 against externally introduced damage such as surface corrosion. It is clear that good planarity is required so that following steps of processing, which frequently use photolithography for patterning and etching of the remaining layer, can expose the surface of layer 16 of dielectric in a uniform way (to for instance avoid depth of focus variations across the surface of layer 16) for, for instance the creation of openings in layer 16 through which contact can be established with patterns 12 and 14.
FIG. 2 shows the cross section of the semiconductor surface 10 of FIG. 1, after the layer 16 of dielectric has been polished. The polishing of layer 16 has, as shown in FIG. 2, left a thin layer of dielectric 16 in place overlying the metal patterns 12 and 14. Also shown in FIG. 2 is the presence of surface irregularities 17, most frequently referred to as surface scratch, that are caused by any interference with a uniform removal of layer 16. Such interference may take the form of slurry irregularities, disturbances or impurities in the surface of the polishing pad and the like. Since irregularities 17 can lead to problems, some of which have previously been highlighted, during subsequent processing of the semiconductor surface 10, these irregularities must be avoided.
FIG. 3 shows a cross section of a semiconductor surface 10, a layer 16 of dielectric has been deposited over the semiconductor surface 10, trenches 11 have been created in the layer of dielectric. A layer 18 of metal has been deposited over the surface of the layer 16 of dielectric, filling the trenches 11 created in layer 16. Layer 10 is typically a semiconductor surface but can also be a layer of insulation. Polishing of the surface of layer 18 of metal, in the case of the invention comprising copper, proceeds by first removing high points form the surface of layer 18 after which the polishing proceeds over the now relatively flat surface of the remaining layer 18 of metal. After the surface of the layer 16 is reached, the abrasive action of the polishing pad and the therewith provided slurry is shared between the metal layer 18 and the surface of the layer 16 of dielectric. The polishing rate of these two surfaces is not equal. In the polishing of a layer 18 of copper, which is addressed by the invention, the copper is removed at a faster rate that the layer 16 of dielectric which, in the application of the invention, comprises a low-k dielectric. This leads to the non-planar or dished surfaces 13 that are shown in cross section for the metal patterns 19 (for a contact pad) and 20 (for interconnect lines).
This effect of a non-uniform removal of the layer of metal 18 versus the layer 16 of interposed low-k dielectric leads to the cross section that is shown in FIG. 5. It is clear from the cross section that is shown in FIG. 5 that the surface level of the copper patterns 19 and 20 is below the surface of the layer 16 of dielectric by a distance 15. The invention addresses a method to achieve good planarity of the surface of layers 16, 19 and 20.
U.S. Pat. No. 6,140,240 (Yang et al.) provide a method for eliminating CMP induced micro scratches but use a compensatory layer of polymer.
U.S. Pat. No. 6,043,149 (Jun) shows an etch back after a copper CMP, see col. 5, line 43. This patent essentially addresses regular metal etch back such as tungsten etch back. This patent however does not address copper CMP applied to damascene structures.
U.S. Pat. No. 6,136,680 (Lai et al.) shows an argon sputter etch after a copper chemical mechanical polish (CMP). This patent does not address the removal of dielectric film scratch.
U.S. Pat. No. 6,010,962 (Liu et al.) shows a cooper chemical mechanical polish (CMP) process with a Low K IMD layer. This patent uses a compensatory layer to address problems of CMP.
U.S. Pat. No. 6,117,775 (Kondo et al.) and U.S. Pat. No. 6,140,240 (Yang et al.) show related processes. These two patents use a compensatory layer to resolve CMP issues, U.S. Pat. No. 6,117,775 (Kondo et al.) uses condition optimization to optimize the slurry condition.
A principle objective of the invention is to reduce post CMP dishing, erosion and micro-scratch on the surface of a low-k dielectric in which is embedded a layer of copper interconnect metal.
Another objective of the invention is to provide a method for creating layers of interconnect metal embedded in a low-k dielectric for sub-micron semiconductor devices by eliminating surface irregularities from the surface of the layer of low-k dielectric.
Another objective of the invention is to provide a method of creating copper interconnect metal for sub-micron devices whereby the interconnect metal is embedded in low-k dielectric capable of providing high yield in fabricating the sub-micron devices.
Another objective of the invention is to provide a method of providing good planarity of a low-k dielectric surface in which patterned copper interconnect metal is provided for sub-micron devices.
In accordance with the objectives of the invention, a new plasma etch back is provided that is applied to the surface of a low-k dielectric after the process of CMP of a copper surface has been completed. The copper surface is the surface of interconnect metal, the interconnect metal is embedded in the layer of low-k dielectric.